1. Field of the Invention
The present invention relates to a high-performance data processor, and more particularly to its repeat processing function.
2. Description of the Background Art
In a digital signal processing and the like, repeat executions of instructions are often made. For effective execution, some DSPs (Digital Signal Processors) have a dedicated instruction and a dedicated hardware.
This is called a block repeat and the like, which repeatedly executes an instruction stream designated by a control register the number of times designated by another register. The block repeat is disclosed in, e.g., Chapters 3, 4 and 5 of xe2x80x9cTMS3209C5x User""s Guide, 1993xe2x80x9d. This function eliminates necessity of counting of the repeat number, judgment on counting result, a branch instruction from the end to the start of repeatedly-executed instructions and the like. The like example is also disclosed in Japanese Patent Application Laid Open Gazette No. 9-212361 (hereinafter, referred to as xe2x80x9copen gazette 1xe2x80x9d).
In the above open gazette 1, a use of block repeat instructions is shown taking an FIR filter as an example (see FIG. 14 of the open gazette 1). Though it is known in advance that the total number of multiply and add operations is 256 in this case, if the total number of multiply and add operations is not known in advance, more complicated processing is required. That requires a complicated program where the quotient obtained by dividing the total number of multiply and add operations by the number 6 of instructions is designated as a repeat number and the remainder is added after the repeat block, though not discussed in detail.
The present invention is directed to a data processor operating in accordance with a program. According to a first aspect of the present invention, the data processor has a step repeat function working in response to a step repeat instruction which is written in the program and can designate first to N-th (Nxe2x89xa72) instructions and an execution instruction number M (Mxe2x89xa71), for repeating the first to N-th instructions K (the quotient of M/N) times and then execute first to L-th (the remainder of M/N) instructions, and the data processor comprises, for the step repeat function: an execution instruction number judgment portion for counting up the number of instruction execution count every time when any one of the first to N-th instructions is executed, to output an instruction execution number judgment result indicating whether an achievement state where the instruction execution count reaches the execution instruction number M or an unachievement state where does not reach; an instruction fetch portion for repeatedly fetching the first to N-th instructions in the order of first, second, . . . N-th, first, second, . . . when the step repeat instruction is executed; and an instruction execution control portion sequentially receiving instructions fetched in the instruction fetch portion, for sequentially executing the instructions received from the instruction fetch portion when the instruction execution number judgment result indicates the unachievement state and for negating the instructions received from the instruction fetch portion when the instruction execution number judgment result indicates the achievement state, in execution of the step repeat instruction.
According to a second aspect of the present invention, the data processor of the first aspect further comprises, for the step repeat function: an information storing portion for storing step repeat instruction execution information indicating whether an executing state where the step repeat instruction is being executed or an unexecuting state where is not being executed, the step repeat instruction execution information being set to the executing state when execution of the step repeat instruction begins, and in the data processor of the second aspect, the instruction fetch portion repeatedly fetches the first to N-th instructions (K+1) times when L is not xe2x80x9c0xe2x80x9d, and sets the step repeat instruction execution information to the unexecuting state when the N-th instruction which is (K+1)th fetched is given to the instruction execution control portion, the execution instruction number judgment portion sets the indication of the execution instruction number judgment result to the achievement state during (K+1)th execution of the L-th instruction, and the instruction execution control portion sequentially negates (L+1)th instruction to the N-th instruction which are (K+1)th executed working in response to the execution instruction judgment result indicating the achievement state.
According to a third aspect of the present invention, the data processor of the first aspect further comprises, for the step repeat function: an information storing portion for storing step repeat instruction execution information indicating whether an executing state where the step repeat instruction is being executed or an unexecuting state where is not being executed, the step repeat instruction execution information being set to the executing state when execution of the step repeat instruction begins; and a timing control portion receiving the execution number judgment result, for generating a control signal indicating fetch of an instruction to be executed after execution of the step repeat instruction with a change of the indication of the execution number judgment result from the unachievement state to the achievement state as a trigger and setting the step repeat instruction execution information to the unexecuting state.
According to a fourth aspect of the present invention, the data processor of the first, second or third aspect further comprises: a block repeat function working in response to a block repeat instruction which can designate an instruction stream consisting of a plurality of instructions and a repeat execution number, for executing the instruction stream repeatedly the repeat execution number of times, independent of the step repeat function.
According to a fifth aspect of the present invention, the data processor of the first, second, third or fourth aspect further comprises: a conditional execution function working in response to an execution condition designating instruction defining a predetermined instruction and an execution condition of the predetermined instruction, for executing/suppressing the predetermined instruction by condition judgment, and the data processor of the fifth aspect further comprises, for the conditional execution function: a condition information storing portion for storing condition information; and an execution condition judgment portion working in response to the execution condition designating instruction, for outputting an execution suppressing signal controlling whether the predetermined instruction is executed or suppressed on the basis of whether the condition information satisfies the execution condition or not, and in the data processor of the fifth aspect, the conditional execution function shares the instruction fetch portion and the instruction execution control portion with the step repeat function, the instruction fetch portion fetches the predetermined instruction in parallel to a judgment operation of the execution condition designating instruction by the execution condition judgment portion, and the instruction execution control portion negates the predetermined instruction given by the instruction fetch portion when the execution suppressing signal indicates suppressing.
Preferably, in the data processor, the step repeat function shares the condition information storing portion with the condition execution function, and the condition information storing portion further stores step repeat instruction execution information indicating whether an executing state where the step repeat instruction is being executed or an unexecuting state where is not being executed.
According to a sixth aspect of the present invention, in the data processor of the first, second, third, fourth or fifth aspect, the first to N-th instructions are sequentially written in the program subsequent to the step repeat instruction, and the step repeat instruction further has address information of the N-th instruction.
Preferably, the step repeat instruction has information specifying a register which stores the execution instruction number.
Preferably, the step repeat instruction has information specifying the execution instruction number.
Preferably, the execution instruction number judgment portion comprises: a number storing portion for storing remaining execution number, the execution instruction number being set to the remaining execution number when execution of the step repeat instruction begins; a counting portion for subtracting xe2x80x9c1xe2x80x9d from the remaining execution number when the remaining execution number is not xe2x80x9c0xe2x80x9d after each execution of the first to N-th instructions, to store a new remaining execution number to the remaining execution number storing portion; and a zero judgment portion for outputting the execution instruction number judgment result on the basis of whether the remaining execution number is xe2x80x9c0xe2x80x9d or not.
In the data processor of the first aspect, the instruction execution control portion sequentially executes instructions received from the instruction fetch portion when the execution instruction number judgment result indicates the unachievement state, and sequentially negates the instructions received from the instruction fetch portion when the execution instruction number judgment result indicates the achievement state, in execution of the step repeat instruction.
Therefore, since the first to N-th instructions fetched in the instruction fetch portion can be surely negated after the total execution number of the first to N-th instructions reaches the execution instruction number, the instructions included in the instruction stream (the first to N-th instructions) can be executed accurately, the designated number of times of the instructions (execution instruction number) while being repeated.
In the data processor of the second aspect, the execution instruction number judgment portion sets the indication of the execution instruction number judgment result to the achievement state during (K+1)th execution of the L-th instruction (M-th executed), and the instruction execution control portion sequentially negates the (K+1)th execution of the (L+1)th to N-th instructions in response to the execution instruction judgment result indicating the achievement state.
Therefore, after the total execution count of the first to N-th instructions reaches the execution instruction number, the (L+1)th to N-th instructions fetched in the instruction fetch portion can be surely negated.
In the data processor of the third aspect, the timing control portion generates the control signal indicating fetch of an instruction to be executed after execution of the step repeat instruction with the change of the indication of the execution number judgment result from the unachievement state to the achievement state as a trigger and sets the step repeat instruction execution information to the unexecuting state.
Therefore, after the total execution count of the first to N-th instructions reaches the execution instruction number, an execution to be executed after execution of the step repeat instruction can be immediately executed.
Since the data processor of the fourth aspect further has the block repeat function, a programmer can use either the block repeat processing or the step repeat processing as required.
In the data processor of the fifth aspect, since the step repeat function and the conditional execution function share the instruction fetch portion and the instruction execution control portion, both the step repeat function and the conditional execution function can be achieved while the hardware cost is reduced to the minimum.
In the data processor of the sixth aspect, the first to N-th instructions are sequentially written subsequent to the step repeat instruction in a program and the step repeat instruction further has an address information of the N-th instruction.
Therefore, when the step repeat instruction is executed, by recognizing the address of an instruction subsequent to the step repeat instruction as the address of the first instruction and the address of the N-th instruction from the address information of the N-th instruction, an address control to execute the first instruction after the N-th instruction in execution of the step repeat instruction.
An object of the present invention is to provide a data processor capable of accurately executing instructions in a predetermined instruction stream the designated number of times of instructions while repeating the instructions.